The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable controlling a supply of termination resistances.
Semiconductor devices are implemented into integrated circuit (IC) chips such as central processing units (CPUs), memories, and gate arrays, and are incorporated into a variety of electrical products such as personal computers, servers and workstations. Most of semiconductor devices include an input circuit configured to receive signals from an outside world via input pads and an output circuit configured to provide internal signals to the outside world via output pads.
As the operating speed of the electrical products is increasing, a swing width of a signal interfaced between the semiconductor devices is being gradually reduced for minimizing a delay time taken for signal transmission. However, the reduction in the swing width of the signal makes the signal easily exposed to external noise, causing the signal reflectance to become more critical at an interface terminal due to impedance mismatch. Such impedance mismatch is generally caused by external noise, a variation of a power supply voltage, a change in an operating temperature, a change in a manufacturing process, etc. The impedance mismatch may lead to a difficulty in high-speed transmission of data and distortion of output data. Therefore, if semiconductor devices receive the distorted output signal through an input terminal, it frequently gives rise to problems such as a setup/hold failure and an error in decision of an input level.
In particular, in order to resolve the above problems, a semiconductor memory device requiring high-speed performance employs an impedance matching circuit, which is called an on-chip termination device or an on die termination (ODT) device, near an input pad inside an IC chip. In a typical ODT scheme, source termination is performed at a transmitting end by an output circuit, and parallel termination is performed by a termination circuit connected in parallel with respect to an input circuit.
FIG. 1 is a block diagram of a conventional semiconductor memory device with an ODT device.
Referring to FIG. 1, the conventional semiconductor memory device includes an ODT driving controller 10, a data pre-driver 20, and a data output buffer 30. The ODT driving controller 10 receives a plurality of ODT setting signals ODT1, ODT2 and ODT3 in synchronization with an external clock CLK and a delay lock loop (DLL) clock RDLLCLK to output a plurality of ODT driving signals ENODT1, ENODT2 and ENODT3 for a predetermined time. The data pre-driver 20 receives falling data DT_F and rising data DT_R to output pull-up data DT_UP and pull-down data DT_DN in synchronization with an external falling clock FCLK and an external rising clock RCLK. The data output buffer 30 applies termination resistances corresponding to the ODT driving signals ENODT1, ENODT2 and ENODT3 into corresponding pads, and drives data corresponding to the pull-up data DT_UP and the pull-down data DT_DN to corresponding pads.
The ODT driving controller 10 includes an input detecting unit 11, a termination determining unit 13, a DLL clock supplying unit 15, a driving signal generating unit 17, and a signal outputting unit 19. The input detecting unit 11 receives the ODT setting signals ODT1, ODT2 and ODT3 and the external clock CLK to generate a period entry signal ODTENB and a driving clock CLKODT. The termination determining unit 13 counts the driving clock CLKODT for a predetermined time in response to the activation of the period entry signal ODTENB to generate a period close signal CLKODTB. The DLL clock supplying unit 15 supplies a plurality of delayed DLL clocks RCLKDLP10, RCLKDLP20, FCLKDLP15 and FCLKDLP25 in response to the period entry signal ODTENB and interrupts the supply of the delayed DLL clocks RCLKDLP10, RCLKDLP20, FCLKDLP15 and FCLKDLP25 in response to the period close signal CLKODTB. The driving signal generating unit 17 receives the ODT setting signals ODT1, ODT2 and ODT3 in synchronization with the external clock CLK in response to the activation of an external ODT signal ODT, and outputs a plurality of pre-driving signals ODTLAT1, ODTLAT2 and ODTLAT3 in synchronization with the delayed DLL clocks RCLKDLP10, RCLKDLP20, FCLKDLP15 and FCLKDLP25. The signal outputting unit 19 drives the pre-driving signals ODTLAT1, ODTLAT2 and ODTLAT3 to the ODT driving signals ENODT1, ENODT2 and ENODT3.
An operation of the conventional semiconductor memory device will be described briefly.
The input detecting unit 11 activates the period entry signal ODTENB when one of the ODT setting signals ODT1, ODT2 and ODT3 is activated. When the period entry signal ODTENB is activated, the input detecting unit 10 outputs the external clock CLK as the driving clock CLKODT.
The termination determining unit 13 is enabled in response to the activation of the Period entry signal ODTENB and counts the driving clock CLKODT to generate the period close signal CLKODTB indicating a predetermined timing when the ODT is disabled.
The DLL clock supplying unit 15 supplies the delayed DLL clocks RCLKDLP10, RCLKDLP20, FCLKDLP15 and RCLKDLP25 in response to the period entry signal ODTENB, and interrupts the supply of the delayed DLL clocks RCLKDLP10, RCLKDLP20, FCLKDLP15 and RCLKDLP25 in response to the activation of the DLL disable signal CLKODTB. The clocks RCLKDLP10, RCLKDLP20, FCLKDLP15 and RCLKDLP25 are generated by delaying the DLL clock.
The driving signal generating unit 17 receives the ODT setting signals ODT1, ODT2 and ODT3 in synchronization with the external clock CLK in response to the activation of the external ODT signal ODT, and outputs the pre-driving signals ODTLAT1, ODTLAT2 and ODTLAT3 in synchronization with the delayed DLL clocks RCLKDLP10, RCLKDLP20, FCLKDLP15 and FCLKDLP25.
The signal outputting unit 19 drives the pre-driving signals ODTLAT1, ODTLAT2 and ODTLAT3 to the ODT driving signals ENODT1, ENODT2 and ENODT3.
The data pre-driver 20 receives the falling data DT_F and the rising data DT_R to output the pull-up data DT_UP and the pull-down data DT_DN in synchronization with the external falling clock FCLK and the external rising clock RCLK.
The data output buffer 30 applies the termination resistances corresponding to the ODT driving signals ENODT1, ENODT2 and ENODT3 into the corresponding pads, and drives data corresponding to the pull-up data DT_UP and the pull-down data DT_DN to corresponding pads.
Whether the termination resistance is supplied or not is determined by detecting a voltage level difference between the corresponding pads.
FIG. 2 is a graph illustrating a voltage level variation of the pad when the termination resistance is supplied to the pad in the semiconductor memory device of FIG. 1.
It can be seen from FIG. 2 that a voltage level in an ODT operating state B, where the termination resistance is supplied, is lower than a voltage level in a floating state A, where no termination resistance is supplied. Due to the supply of the termination resistance, the voltage level of the pad, i.e., a pin, is dropped.
Therefore, whether the termination resistance is normally supplied or not is determined by detecting the voltage drop of the pads. This is because the control for termination resistance cannot be visually verified in the design.
As the range of the external voltage becomes narrow, the range of the voltage drop also becomes narrow and thus the detection of the voltage drop is difficult. Further, when the malfunction should be practically corrected in a design, its measurement is impossible and it cannot be corrected promptly. Thus, it will take a lot of time to analyze a defective device.